This invention relates generally to high-speed output driving circuits and more particularly, it relates to a supply bounce controlled output buffer circuit in integrated circuits which has a significant reduction in inductive ringing.
As is well-known in the art, digital logic circuits are widely used in the areas of electronics and computertype equipment. Specifically, one such use of digital logic circuits is to provide an interface function between one logic type of a first integrated circuit device and another logic type of a second integrated circuit device. An output buffer circuit is an important component for this interface function. The output buffer circuit provides, when enabled, an output signal which is a function of a data input signal received from other logic circuitry of the integrated circuit.
In FIG. 1, there is shown a simplified schematic circuit diagram of a portion of a typical output buffer circuit 10 which is formed as part of a semiconductor integrated circuit chip 12. The output buffer circuit 10 includes a pull-up transistor device 14 and a pull-down transistor device 16 connected in series between respective first and second power supply terminal pins 18, 20. The first power supply terminal pin 18 may be supplied with a positive potential or voltage VCC (typically at +5.0 volts) which is connected to an internal power supply potential node VL2 via a lead line having parasitic inductance L2. The source of the P-channel field-effect transistor 14 is also connected to the node VL2. The parasitic inductance L2 represents a package inductance associated with the terminal pin 18 itself and the bond wire used to connect the source of the transistor 14 to the terminal pin 18. The second power supply terminal pin 20 may be supplied with a ground potential VSS (typically at 0 volts) which is connected to an internal ground potential node VL1 via a lead line having parasitic inductance L1. The source of the N-channel field-effect transistor 16 is also connected to the node VL1. The parasitic inductance L1 represents a package inductance associated with the terminal pin 20 itself and the bond wire used to connect the source of the transistor 16 to the terminal pin 20.
The drains of the transistors 14 and 16 are connected together and are further joined to an internal node 22. The internal node 22 is also connected to an output terminal pin 24 via a lead connection having parasitic inductance L3. The parasitic inductance L3 represents a package inductance associated with the output terminal pin 24 itself and the bond wire used to connect the drains of the transistors 14, 16 to the terminal pin 24. The output of the terminal pin 24 of the buffer circuit 10 is used to drive a capacitive load represented by capacitor CAP and connected between the terminal pin 24 and the ground potential VSS. The capacitor CAP defines the load that the output terminal pin sees and is the sum of individual capacitances of all the devices being driven as well as the board capacitance.
Dependent upon the logic state of the data input signal and an enable signal, either the pull-up transistor 14 or the pull-down transistor 16 is quickly turned OFF and the other one of them is turned ON. Such rapid switching OFF and ON of the pull-up and pull-down transistor devices causes sudden surges of current creating what is commonly known as current spikes. As a result, when the internal output node 22 is making a high-to-low transition, oscillation or inductive ringing appears at the output terminal 24 referred to as "ground bounce." This "ground bounce" is defined to be undershooting of the ground potential followed by a dampening oscillation around it. This is a major problem in highspeed output buffer circuits. The higher the value of the inductance and the lower the value of the capacitance, the more severe will be the "ground bounce."
Also, during such output switching, charging and discharging currents from the pull-up and pull-down transistor devices will flow through the package inductances of the power supply and ground lines so as to cause inductive noises at the internal power supply potential node VL2 and at the internal ground potential node VLl. These internal supply and ground noises are undesirable since they will degrade the output voltage levels (logic "1" and logic "0) causing interface problems among the output buffer circuit and other integrated circuits.
Referring again to FIG. 1, assume initially that the output terminal pin 24 is at a positive voltage or logic "1" level. In order to have a high-to-low transition occur at the output terminal pin 24, the pullup transistor 14 is turned off and the pull-down transistor 16 is turned on. As a result, as the pull-down transistor 16 begins to conduct, the voltage at the internal ground potential node VL1 will jump up momentarily from the ground potential due to a higher voltage connected to it from the output terminal pin 24. This will, in turn, cause the pull-down transistor 16 to lose momentarily some of its driving power thereby slowing down the rate of the transition at the output terminal pin 24. When the inductor finally does change state, this voltage at the node VL1 will then go down and the transistor 16 will start pulling down the output pin 24 at a high transition rate again. The harder (faster) the transistor 16 turns on, the voltage jump at the node VL1 will be more exaggerated or severe. For example, a best case process corner (fast) transistor will turn on and pull down faster than a worst case process corner (slow) transistor.
While the pull-down transistor 16 will begin to turn off as the voltage at the output terminal 24 approaches ground (0 volts), the potential energy developed in the inductive and capacitive components (L3 and CAP) will cause this voltage to undershoot the ground potential. Consequently, the pull-down transistor 16 will be turned on in the reverse direction so as to couple the potential energies in the inductances L3 and L1 in a mutually aiding manner. As a result, the voltage on the output terminal will undershoot even further than it had intended thereby aggravating the ringing. Thus, there will be several oscillations occurring before the voltage at the output terminal 24 reaches the steady-state condition.
Similarly, when the output terminal 24 is making a low-to-high transition inductive ringing will appear at the output terminal and the output voltage will overshoot the positive supply potential. This overshoot is sometimes referred to as "supply bounce."
The present invention utilizes the voltage jump at the internal power supply potential and ground potential nodes VL2 and VL1 to slow down the rate of transition at the output terminal 24, thereby reducing significantly the inductive ringing. This is achieved by the provision of first and second delay networks for turning off the corresponding pull-up or pull-down transistor earlier than it would normally turn off so as to slow down the rate of rise or fall of the output signal for the portion of the time when the output terminal pin is making the corresponding low-to-high or high-to-low transition.